1. Field of the Invention
The present invention relates to the field of communications, and more particularly, to a byte aligner and frame synchronizer for data transmission of 622 Mbit/s used in high-speed data communication systems.
2. Description of Related Art
Today, high speed data communication requires a byte aligner and frame synchronizer which can accomodate high speed data such as data of 622 Mbit/s rate or higher.
The conventional frame synchronizers are commonly used for data of 155 Mbit/s rate or lower. But, applied to high speed data communication, such a frame synchronizer needs a long synchronization time, more hardware and high-priced manufacture because of its structural problems. Explaining in more detail, since it has to perform frame synchronization using all of the frame bytes, the conventional frame synchronizer has to wait for all of the frame bytes and this needs a considerably long time to effect frame synchronization. In addition, since it processes data serially, for accommodating 622 Mbit/s data, such a frame synchronizer needs more hardware and high-priced manufacture.
Therefore, seen in view of performance and economy, the conventional frame synchronizer is not appropriate for application to 622 Mbit/s data.
In general, in high speed data communication such as time-division multiplex of synchronous transport module-4 concatenation (STM-4C), data is transmitted by a frame unit with a period of 125 .mu.sec which data is not only allocated sequentially to the corresponding time slots but twenty-four frame bytes are also inserted in the data stream every 125 .mu.sec. Then, at the receiver, frame synchronization is acquired by extracting the frame signal from received data according to a pre-defined rule.
According to the ITU-T standard, the frame format for STM-4C is as follows: twelve A1 bytes stream whose binary bits are 11110110 and continuously twelve A2 bytes stream whose binary bits are 00101000. In addition, such frame bytes are defined to place in the front position of STM-4C data stream.
Fujimoto's U.S. Pat. No. 4,748,623 disclosed only frame synchronization and serial-to-parallel conversion without byte alignment. According to this disclosure, this device confirms whether the frame sync pattern is present or not in the received data, and then once present, it extracts a frame pulse from the received data and makes a timing control signal for a frame pulse. Such a timing control signal adjusts the liming of received data to acquire a frame synchronization correctly.
However, since it requires such complex processes and is invented for 155 Mbit/s, for applying to the frame synchronization for 622 Mbit/s data, this disclosure has disadvantages that it increases the clock frequency and the amount of hardware. In addition, it needs more precise byte alignment hardware to prevent byte alignment error during serial-parallel conversion.
Another conventional art, which is disclosed in U.S. Pat. No. 4,748,623, acquires frame synchronization using a parallel processing method. After this disclosure detects the frame synchronization pattern, it compares its timing using a timing comparator and synchronization protection circuit and then adjusts the timing of the frame synchronization by a timing controller.
But, because of not having the frame error control function, detecting the analogous pattern with the frame pattern, this disclosure operates automatically unnecessary processes such as frame synchronization and timing adjustment. Thus, because it is liable to malfunction by an analogous frame pattern, this disclosure is not appropriate for 622 Mbit/s data in which can occur more analogous frame patterns than in lower speed data.
For still another reference, there is a paper by DooWhan Choi entitled "Frame alignment in a digital carrier system" (hereinafter referred to as paper 1) in IEEE comm. magazine (Feb. 1990). Paper 1 deals with frame alignment in the digital carrier system with an added-bit frame and burst frame, and suggests simulation results of acquisition time and loss time in frame synchronization. However, paper 1 presents only ideal conditions and ideal values for improving the performance of frame synchronization, but has no specific implementation for frame synchronization.
For a further reference, there is a paper (hereinafter referred to as paper 2) by Lin Xiaokang entitled "A new design of the STM-1 frame aligner" in ECC'93. Paper 2 shows the method of frame synchronization in the STM-1 frame structure. That is, this paper describes the method of frame synchronization acquired by searching the A1A1A2 pattern among eight frame bytes using parallel processing. But, since this paper describes technologies for 155 Mbit/s data only, it is not appropriate to apply this technique to frame synchronization for 622 Mbit/s data.